1. Field of Invention
The present invention relates to a power amplifier, and in particular to a power amplifier, a power amplifier circuit, and an amplifying method, which reduces a voltage drop across a transistor by adjusting a bias voltage.
2. Description of Related Art
In wireless communication devices, various power amplifiers are utilized to amplify a signal to be transmitted. Among these power amplifiers, a metal oxide semiconductor field effect transistor (MOSFET) power amplifier is typically used in the communication devices to amplify a signal because of its features such as low cost and high integrity.
However, when the FET functions as an amplifier for a radio frequency (RF) input signal, its lifetime is reduced due to damages such as hot carrier effects and breakdown of an oxide layer in the transistor caused by its high bias voltage and a high peak value of the RF signal. Further, these adverse effects are more serious as the transistor is made smaller and the channel is shorter in more advanced semiconductor processes. To overcome such problems, a power amplifier having two transistors arranged in a cascode configuration is proposed in the article entitled “A 2.4 GHz 0.18 um CMOS Self-Biased Cascode Power Amplifier with 23 dBm Output Power,” by Sowalti and D. Leenaerts and published in ISSCC Dig. Tech. Papers, pp. 294-295, February, 2002. FIG. 5 shows such an power amplifier 200 having two MOSFETs 202 and 204 arranged in a cascode configuration. In general, the MOSFET 204 functions as a common gate transistor so as to provide an output terminal to an amplified signal, its gate normally receives a DC bias voltage such as 3.3 V, and it sustains a high voltage difference Vds (drain to source) if an input signal has a high power. The MOSFET 202 functions as a common source transistor and its gate receives a DC bias voltage (not shown in the figure) and the RF input signal vrf. Since there are two transistors in such a configuration, the damage to the transistors caused by the peak values of the input signal can be reduced. For example, the amplifier 200 according to the prior art may generate a voltage drop up to 6 volts across the drain and the source in the MOSFET 202, but a MOSFET fabricated by a 65 nm semiconductor process can only endure a voltage drop of about 1.2 volts (V) across the drain and the source. Therefore, the transistor such as the MOSFET 202 in the power amplifier is likely to be damaged by the high voltage drop and accordingly its lifetime and reliability are reduced.
Further, in the U.S. Pat. No. 6,784,740, a power amplifier using a feedback technology is disclosed. FIG. 6 shows the power amplifier of this patent document, which is a combination of a feedback circuit and the circuit shown in FIG. 5. The feedback circuit 330 receives a RF input signal at its positive input terminal, and its negative input terminal is connected to an output terminal Out. The output terminal of the feedback circuit 330 is connected to the gate terminal of the FET transistor 310 for adjusting its bias voltage so that power consumption is reduced for a low power input signal and linearity is improved for a high power input signal. However, in such a prior art circuit, the damage to the transistor functioning as the common source caused by the high voltage drop across the drain and the source is not prevented, and no protection function for the transistor is provided.
Therefore, it is desirable to provide a power amplifier that can effectively reduce the voltage drop across the drain and the source of the transistor functioning as the common source in the power amplifier in order to improve reliability and lifetime of the power amplifier.